1. Field of the Invention
The invention relates to a circuit substrate and a process for fabricating the same. More particularly, the invention relates to a circuit substrate that may be applied in a semiconductor package and a process for fabricating the circuit substrate.
2. Description of Related Art
In accordance with the existing semiconductor packaging technology, chip carriers are commonly used for the interconnection between integrated circuit (IC) chips and the next-level electronic devices, such as motherboards, module boards, or the like. A circuit substrate is often employed in the chip carrier with high I/O count. A conventional circuit substrate is mainly composed of a plurality of patterned conductive layers and a plurality of dielectric layers alternately stacked to one another. In addition, the patterned conductive layers are electrically connected through a plurality of conductive vias.
A flip-chip bonding process is a packaging process applicable to the IC chip with high I/O count; by performing the flip-chip bonding process, the IC chip may be connected to the circuit substrate through a plurality of conductive structures arranged as an area array. However, in a process for fabricating the conductive structures, openings of a patterned photoresist layer are required to communicate with and completely expose openings of a dielectric layer. Hence, when the openings of the patterned photoresist layer are formed, the requirement for alignment accuracy poses a limitation on formation of the openings of the patterned photoresist layer, and thereby a width of the openings of the patterned photoresist layer need be greater than a width of the openings of the dielectric layer or a solder resist layer. As such, the size of the openings of the patterned photoresist layer cannot be reduced, and nor can the dimensions and bump pitches of conductive bumps. Moreover, since the bump pitches are unlikely to be shortened, pitches among chip pads on the chips cannot be correspondingly shortened.